Hey, folks. I've been working on a test ROM that can be run on the real PCE and emulators, to test for correct CPU instruction timing, as well as VRAM/VDC access. I'll release it soon, but first if anyone wants to try it out and report bugs or suggestions for improvement, please do.
I ran this demo from an 8M flash HuCard that has no menu software, to get a baseline for authenticity. To my surprise, running it from an Everdrive or SDSS3 gave quite different results in the final block transfer (X-cycles) stage. My demo relies on VBlank for end-of-frame timing, then CPU cycle counts its way down the screen. Emulators like Mednafen seem to have their timing off just a bit, as seen by the raster lines showing up ~24 pixels too far to the right. (There are other weird things going on with the VDC if the block transfer instructions start near the right side of the screen, but I'll bring that up later.)